1. Field of the Invention
The present invention relates to a semiconductor structure; in particular, to a semiconductor structure with low power consumption.
2. Description of Related Art
In applications of power metal-oxide semiconductors (power MOS), electrical specifications and heat dissipation capability are among the most critical. The primary factor that influence the electrical specifications and the heat dissipation capability of the power MOS is drain-source on-resistance Rds(ON), which generally consists of conducting resistance of the power MOS die and resistance formed in the packaging process of the power MOS. As it is well known that a minimized Rds(ON) corresponds to the superior heat dissipation capability and electrical specification of the power MOS, how to decrease both the conducting resistance and the resistance associated with the packaging has been one of challenges facing in the power MOS industry.
When a substrate 101 of a traditional vertical power MOS, shown in FIG. 1, takes up over 90% of the size of a power MOS chip in terms of thickness, however, percentage of the resistance of the substrate in view of the resistance of the power MOS chip would increase as working voltage of the power MOS chip is decreased. For example, the resistance of the substrate ranges from 3 percents to 5 percents of the resistance of the power MOS chip with 600V working volts. Meanwhile, for the power MOS with less than 30V working voltage, the resistance of the substrate would be increased to 15 percents to 30 percents of the power MOS chip. A traditional method of decreasing the resistance of the substrate is to grind the power MOS chips from 300 μm to 50 μm, as shown in FIG. 2. FIG. 2 shows the structure of the vertical power MOS with grinded substrate. The power MOS chips with the grinded substrates are so thin and subject to being broken frequently during subsequent semiconductor packaging process. In order to protect such thin chips, extra process and equipment become necessary. It results in significant increase in cost. Such thin chips are likely associated with the micro crack, which cause significant reduction in life-time of the usage. Therefore, how to improve the power semiconductor with low Rds(ON) effectively, and to cut down the associated cost, as well as to minimize the likelihood of the micro crack on chip have been important issues.
Accordingly, the invention provides a semiconductor structure with low drain-source on-resistance (Low Rds(ON)) in order to overcome the disadvantages of the related art.